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X(52) ... ... ... x(4) x(3) x(2) x(1) d 45 ... 26th-order statistic k=3 33th-order statistic k=4 (b) 45 d 81 ... d 49 x(12) ... x(1) d 48 ... ... d1 d 69 ... d 48 x(20) ... Minimum k=1 x(2) x(1) d47 ... ... 2nd-order statistic k=2 d1 d1 3rd-order statistic k=3 4th-order statistic k=4 d1 (c) Figure 12. (a) Structuring element, (b) arrangement of the dummy numbers in soft morphological dilation using the structuring element of (a), and (c) arrangement of the dummy numbers in soft morphological erosion using the same structuring element.
MUX1 L2 Adder . . . L2 Adder ... s1 L*1 . . s9 XNORs C in d1 L2 . . . . . L*1 XNORs L2 from the adder corresponding to the core pixel. p1 d8 L3 L4 . . . L3 L4 ... MUX2 L3 L4 . . . . . MUX2 L3 L4 . . . . . L11 ... L11 . . . L11 ... PE i1... i8 L**1 F/F L2 F/F CONTROL UNIT b9 b1 r0 MODE L11 ... k . . r1 t 1 L**4 . . r8 t 8 L**11 o1 PE o8 L*4 . . o9 L*11 pi : image data si : structuring element data di :dummy numbers Figure 10. Systolic array hardware structure implementing the majority gate technique for soft morphological ﬁltering.
The resolution of the latches, which hold the addition/subtraction results or the dummy numbers (L3 to L11), decreases by 1 bit at each successive stage, because there is no need to carry the bits, which have been already processed. On the other hand, the resolution of the latches that hold the result (L4∗ to L∗ 11), increases by 1 bit at each successive stage. The circuit diagram of this PE is shown in Figure 11. In this ﬁgure W = 4N + 1; the 2N + 1 inputs are the numbers xi, whereas the rest b1, j r 1 , j +1, bW«, j r W «, j+1 r 1, j t 1, j+1 r W «, j tW «, j+1 t1, j - ri,j the rejecting flag signals - ti,j the setting flag signals - ii,j intermediate signals - bi,j the binary representation tW «, j i 1, j * iW «, j oj o j +1 of the inputs * Majority gate Figure 11.