By Eva M. Ortigosa, Antonio Cañas, Eduardo Ros, Richard R. Carrillo (auth.), José Mira, José R. Álvarez (eds.)
The two-volume set LNCS 2686 and LNCS 2687 represent the refereed complaints of the seventh overseas Work-Conference on synthetic and traditional Neural Networks, IWANN 2003, held in Ma?, Menorca, Spain in June 2003.
The 197 revised papers provided have been rigorously reviewed and chosen for inclusion within the e-book and handle the subsequent issues: mathematical and computational equipment in neural modelling, neurophysiological info research and modelling, structural and useful types of neurons, studying and different plasticity phenomena, advanced platforms dynamics, cognitive approaches and synthetic intelligence, methodologies for web layout, bio-inspired platforms and engineering, and purposes in a large number of fields.
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Extra resources for Artificial Neural Nets Problem Solving Methods: 7th International Work-Conference on Artificial and Natural Neural Networks, IWANN2003 Maó, Menorca, Spain, June 3–6, 2003 Proceedings, Part II
M. G. Ferreira and F. M. G. Franl;a, "Weightless implementations of weighted neural networks," Proc. of the IV Brazilian Symposium on Neural Networks SBRN'97, Goiania, GO, Brazil, vol. II, 53-54 (1997). 3. W. S. McCulloch and W. Pitts, "A Logical Calculus of the Ideas Immanent in the Nervous Activity," Bull. Math. Bioph. 1943. 4. A. Aiello, E. Burattini, G. Tamburrini, "Purely Neural, Rule-Based Diagnostic Systems. Part I: Production Rules," International Journal of Intelligent Systems, 10,735-749 (1995).
Weights (8 bits). Input to the activation function. The activation function is defined by a Look-UpTable (LUT), but we have to specify how to store the useful values. In order to choose the bit precision of these values we have to take into account the maximum value reachable with the weighted sum of a neuron inputs. As the maximum number of entries to a neuron is 220, the maximum absolute value reachable with the weighted sum of a neuron inputs will be 3548380 (result of 127(max. input) x 127(max.
The parallel designs have been defined through the Handel-C "par" directive that forces the implementation of dedicated circuits for a certain part of an algorithm to be computed in parallel. But it must be noted that since the designs have been defined using a high level Hardware Description Language the automatic synthesis pathway is long and optimizations in the DKI compiler or the Xilinx synthesis tool may affect the design characterizations shown in Tables 1 and 2. 5 microseconds per sample, which fulfills by far the time restrictions imposed by the application.