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Extra resources for Arithmetic Built-In Self-Test for Embedded Systems
10: Weighted pattern generator. the LFSR-based pseudo-random test generators by biasing the probabilities of the input bits so that the tests needed for hard-to-test faults are more likely to occur. This concept is illustrated by the circuit shown in Fig. 10b. 5 of being either a 0 or a 1. More precisely, the probability of having 1 is 2 n - 1 / ( 2 n — 1), where n is the size of the LFSR. Let us also assume that these events are statistically independent of which states occur on other bits. 5k.
Built-in Self-Test test vectors are applied from the test-pattern generator (TPG) and test re sponses are captured in test-response compactor (TRC) every clock cycle. No tice that the scheme introduces a performance degradation due to the presence of multiplexer between the primary inputs and the CUT. In test-per-scan BIST (Fig. 17b), test vectors are shifted into a serial scan path, applied to the CUT, and test responses are subsequently captured in the scan flip-flops and shifted out to the TRC while a new test is being shifted in.
Details of techniques based on structural analysis and deterministic test sets can be found, for instance, in , , , , , , and . 5 Reseeding of Linear Feedback Shift Registers An efficient test generation scheme is expected to guarantee a very high fault coverage while minimizing test application time and test data storage require ments. 3. Generation of Test Vectors 25 or weighted-random patterns, schemes based on these vectors may not be able to detect some faults in some circuits in a cost-effective manner.