By Junjie Wu, Haibo Chen, Xingwei Wang
This e-book constitutes the refereed court cases of the tenth Annual convention on complicated desktop structure, ACA 2014, held in Shenyang, China, in August 2014. the nineteen revised complete papers awarded have been conscientiously reviewed and chosen from one hundred fifteen submissions. The papers are prepared in topical sections on processors and circuits; excessive functionality computing; GPUs and accelerators; cloud and information facilities; power and reliability; intelligence computing and cellular computing.
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Additional resources for Advanced Computer Architecture: 10th Annual Conference, ACA 2014, Shenyang, China, August 23-24, 2014. Proceedings
The model simplifies cache coherence for the full chip, and reduces cache design complexity. In addition, the model has the ability to describe the direct exchange of data on chip, thereby alleviating the off-chip memory bandwidth requirements. The paper gives a formal definition of the model, and proves that the model is sequentially consistent. All aspects of the definition are fully used in the process of proof, which means that there is no redundancy in the definition. Therefore, based on the split-range shared memory consistency model, a shared memory system can achieve high performance at low hardware cost.
Xie Since both TMLSei a and TMSiSe a are atomic operations, it follows that the SRS model extended for global data still satisfies the ordered pair condition. Therefore, the SRS model is still sequentially consistent after being extended for global data. 6 Conclusion The paper completes the formal description of the SRS model and the proof of sequential consistency. The above proof shows that the model is complete, correct and usable. Different from traditional memory consistency models(such as SC, TSO/X86, RMO), the SRS model simplifies cache coherence for the full chip, and reduces design complexity, which is suitable for thousand-core processors.
Blindly increasing of the bandwidth also cannot break through the upper bound. The MMV1 is an example. MMV1 Hydro 250 200 150 100 50 0 1/1 2/1 4/1 ∞/∞ Memory access buses Fig. 7. Performance relative to the memory bandwidth 6 Conclusions In this work, a novel reconfigurable architecture named ACRP is proposed for specific domain. The ACRP contains two types of PE, SPE and CFU. The SPEs which execute basic operations are organized into a linear structure. And the CFU is customized according to the domain computing characteristic, which specially executes the frequent instruction sequence of the domain.